Fault Tolerant Electronic System Design

Due to technology scaling, which means reduced transistor size, higher density, lower voltage and more aggressive clock frequency, VLSI devices may become more sensitive against soft errors. Especially for those devices used in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena (e.g., aging and wear-out effects) also have negative impacts on reliability of modern circuits. Recent researches show that even at sea level, radiation particles can still induce soft errors in electronic systems. On one hand, processor-based system are commonly used in a wide variety of applications, including safety-critical and high availability missions, e.g., in the automotive, biomedical and aerospace domains. In these fields, an error may produce catastrophic consequences. Thus, dependability is a primary target that must be achieved taking into account tight constraints in terms of cost, performance, power and time to market. With standards and regulations (e.g., ISO-26262, DO-254, IEC-61508) clearly specify the targets to be achieved and the methods to prove their achievement, techniques working at system level are particularly attracting. On the other hand, Field Programmable Gate Array (FPGA) devices are becoming more and more attractive, also in safety- and mission-critical applications due to the high performance, low power consumption and the flexibility for reconfiguration they provide. Two types of FPGAs are commonly used, based on their configuration memory cell technology, i.e., SRAM-based and Flash-based FPGA. For SRAM-based FPGAs, the SRAM cells of the configuration memory highly susceptible to radiation induced effects which can leads to system failure; and for Flash-based FPGAs, even though their non-volatile configuration memory cells are almost immune to Single Event Upsets induced by energetic particles, the floating gate switches and the logic cells in the configuration tiles can still suffer from Single Event Effects when hit by an highly charged particle. So analysis and mitigation techniques for Single Event Effects on FPGAs are becoming increasingly important in the design flow especially when reliability is one of the main requirements

On the Mitigation of Single Event Transients on Flash-based FPGAs

Thanks to the immunity against Single Event Upsets in configuration memory, Flash-based FPGA is becoming widely adopted in mission- and safety-critical applications, such as in aerospace field. However, the decreasing of device feature size leads to an increasing of the device sensitivity regarding Single Event Transients (SETs). In this paper, we developed a new workflow to evaluate SET phenomena in a specific convergence case and introduce a new mitigation of SET pulse without introducing any performance penalization to the original netlist

SETA-RAY: A New IDE tool for Predicting, Analyzing and Mitigating Radiation-induced Soft Errors on FPGAs

One of the main concern for FPGA adopted in mission critical application such as space and avionic fields is radiationinduced soft errors. Therefore, we propose an IDE including two software tools compatible with commercial EDA tools. Rad-Ray as the first and only developed tool capable to predict the source of the SET phenomena by taking in to account the features of the radiation environment such as the type, LET and interaction angle of the particles, the material and physical layout of the device exposed to the radiation. The predicted source SET pulse in provided to the SETA tool as the second developed tool integrated with the commercial FPGA design tool for evaluating the sensitivity of the industrial circuit implemented on Flash-based FPGA and mitigate the original netlist based on the performed analysis. This IDE is supported by ESA and Thales Alenia Space. It has been applied to the EUCLID space mission project that will be launched in 2021

On the Mitigation of Single Event Transient in 3D LUT by In-Cell Layout Resizing

We propose a workflow for the analysis and mitigation of 3D ICs to Single Event Transient by upsizing the sensitive transistors. The workflow is applied to 45-nm 3D LUT and the results show a 37% reduction in failure rate

An Automated Continuous Integration Multitest Platform for Automotive Systems

Testing has always been a crucial part of application development. It involves different techniques for verifying and validating the features of the target systems. For a complicated and/or complex system, tests are preferred to be carried out in different stages of the development process and as early as possible to avoid extra costs due to the errors caught at later stages. With the increasing system complexity, the cost of testing is also increasing in terms of resources and time, which introduce further impact against development constraints such as time-to-market. On the other hand, more and more associated electronic components lead to an ever-increasing system complexity in high reliable applications such as automotive ones different from heterogeneous systems such as advanced driver assistance systems, sensor fusion systems, etc. In this article, we present a testing framework utilizing the continuous integration (CI) solution from software engineering, a commercial virtual platform, and a hardware field programmable gate array based verification platform focusing on the engine control unit to demonstrate the feasibility of the proposed method. The efficiency and viability of the CI method have been demonstrated on a real heterogeneous automotive system

A new Method for the Analysis of Radiation-induced Effects in 3D VLSI Face-to-Back LUTs

In recent years, three-dimensional IC (3D IC) has gained much attention as a promising approach to increase IC performance due to their several advantages in terms of integration density, power dissipation and achievable clock frequencies. However, the reliability of 3D ICs regarding soft errors induced by radiation is not investigated yet. In this work, we propose a method for evaluating the sensitivity of 3D ICs to Single Event Transient induced by Heavy Ions. The flow starts with identifying the characteristics of the generated transient pulses with respect to the radiation profile and 3D layout of the design. Secondly, our method provides a Dynamic Error Rate using a Simulation-based Fault Injection environment. Experimental results achieved applying the approach on a 15nm 3D configurable Look-Up-Table (LUT) designed on two tiers demonstrated the feasibility of the method, showing the vulnerability characterization of four different functional configurations using eight different types of heavy ions

Programmers manual FlexGripPlus SASS SM 1.0

This document describes the op-code of the assembly language SASS of the G80 architecture used in the FlexGripPlus model. Every instruction is compatible with the CUDA Programming environment under the SM_1.

Analyzing Radiation-Induced Transient Errors on SRAM-Based FPGAs by Propagation of Broadening Effect

SRAM-based field programmable gate arrays (FPGAs) are widely used in mission-critical applications, such as aerospace and avionics. Due to the increasing working frequency and technology scaling of ultra-nanometer technology, single event transients (SETs) are becoming a major source of errors for these devices. In this paper, we propose a workflow for evaluating the behavior of SETs in SRAM-based FPGAs. The method is able to compute the propagation-induced pulse broadening (PIPB) effect introduced by the logic resources traversed by transient pulses. Besides, we developed an accurate look-up table (LUT) layout model able to effectively predict the kinds of the SETs induced by radiation-particle and to accurately mimic the phenomena of the SET generation and propagation. The proposed methodology is applicable to any recent technology to provide the SET analysis, necessary for an efficient mitigation technology. The experimental results achieved from a set of benchmark circuits mapped on a 28-nm SRAM-based FPGA and compared with the fault injection experiments demonstrate the effectiveness of our technique